SiliconAid Solutions DFT Course Outline

Presented by "Ben" Bennetts, Bennetts Associates and Jim Johnson, SiliconAid Solutions, Inc.

DURATION: 2 days

TARGET AUDIENCE: digital chip designers and test engineers, test-synthesis tool developers and product support engineers.

MOTIVATION OBJECTIVES: to motivate chip designers to consider life-cycle test needs as an integral part of a product design process to the point where they proactively seek help to design in testability.

TEACHING OBJECTIVES: determine the fundamental limits of test technology and hence identify the "why" of DFT; teach the "how" of DFT solutions - internal scan and Built-In Self Test and demonstrate the tools in action


Day 1 is a general introduction to the notional concepts of Design-For-Test and its relationship with device life-cycle test and overall quality requirements. The day starts with a refresher on the basics of DFT covering the classic fault models (stuck-ats, bridging and propagation delay) and their relevance to modern-day silicon defects. This is followed by a brief introduction to IDDQ current test. But the bulk of the day is devoted to the DFT technique of internal scan: where it came from, what it is, and an in-depth look at the practical issues based on using commercial tools. The day concludes with a review of practical DFT guidelines to support scan design.

• DFT, quality and test
• IC defects and fault models
• IDDQ Testing

• ATPG: Sensitive path concepts (combinational and sequential application)
• Assessing fault coverage: fault simulation
• Reasons for and principles of scan design
• Edge-Sensitive Scan Design: MDFF
• PLD design example

• Rule checking: identifying candidate flip-flops for scan chain insertion
• Scan-chain balancing
• Single or multiple clock in scan mode?
• Module-to-module scan chain linking
• Multi-cycle paths and false paths
• Flip-flop ordering/reordering in scan chains
• Handling embedded memory: wrapper, bypass and write through
• Scan chain insertion
• DEMONSTRATION – Simple design performing scan insertion and quick ATPG
• Adding disabling logic to avoid contention during scan-in/out operation
• Designer responsibilities
• The major pros and cons of scan based design

• The does and don’t of making a "Scan Friendly" Design
• How to work around some common real world circuits (clock gating, tri-state busses, and more)

• Common types of DRCs third party tools check
• DEMONSTRATION - Execute the same basic design as shown earlier; however, this version has a few common DRC violations.

Day 2 continues on some of the more recent developments in internal scan and then concentrates on Built-In Self Test, looking at the two main industrially-accepted Built-In Self Test techniques of memory BIST (for multiple instances of embedded memory) and logic BIST (as a natural extension of full scan circuits). The day concludes with a discussion of the recent test-data compression techniques, and how they stack up against logic BIST, and the emergence of the PC-based low-cost DFT testers

• What causes delay faults?
• How are they modelled?
• Pattern generation techniques
• Methods for selecting Paths to target with Path delay vectors
• Pattern application techniques (through scan chain)

• Elements of a BIST circuit
• Motivation for and potential benefits of BIST
• RAMs: failure mechanisms and test algorithms (6N, 9N, March C-, ….)
• Memory BIST (SRAM, DRAM, ROM)
• Architecture for multiple instances of memory
• DEMONSTRATION – Simple memory BIST with multiple arrays on one controller
• Logic BIST: BIST for scan design ICs
• Use of pseudo-random pattern generation and data compaction techniques: pseudo-random properties, aliasing
• Building blocks: Linear Feedback Shift Register (LFSR) and Multiple-Input Signature Register (MISR)
• Logic BIST architecture
• DEMONSTRATION – Full scan design performing Logic BIST
• At-speed testing thru logic BIST
• Overcoming pseudo-random resistance: test-point insertion, re-seeding
• Scan-thru-TAP mode

• What is test data compression?
• Compression/decompression techniques
• Logic BIST versus test data compression

• The emergence of the low-cost PC-based chip tester for DFT-enabled devices

• DFT economics
• Leveraging DFT techniques "above the chip" and "above the board": product life-cycle view

Dr R G "Ben" Bennetts is an independent consultant in Design-For-Test (DFT), consulting in product life-cycle DFT strategies, and delivering on-site and open educational courses in DFT technologies.

Previously, he has worked for LogicVision, Synopsys, GenRad and Cirrus Computers. Between 1986 and 1993, he was a free-lance consultant and lecturer on Design-for-Test (DFT) topics. During this time, he was a member of JTAG, the organization that created the IEEE 1149.1 Boundary-Scan Standard. He is an Advisory member of the Board of Directors of ASSET InterTech and a member of Teseda’s Technical Advisory Board.

Ben has published over 90 papers plus three books on test and DFT subjects.

Jim Johnson founded SiliconAid Solutions, Inc. in 2001. Jim has over fifteen years experience in the semiconductor industry, focused on Design-for-Test and manufacturing test challenges. Jim has extensive DFT expertise in all related areas of test, design, and Design-for-Test.

Jim has gained experience through positions with National Semiconductor Inc., Motorola Semiconductor Inc., and Mentor Graphics Corp. Jim has proven his ability to be an effective bridge between management, design, test, DFT, failure analysis and manufacturing engineering teams. His broad background gives him the ability to identify and correct problem root causes quickly and efficiently, independent of tools or methods