SW DFT Conference seeks 6 - 10 quality papers on the latest trends and thinking in the design for test and test engineering fields. Moore's law, while bearing down on the limitations of physical constraints, has succeeded in shifting the focus of test for complex IC's away from the functional and into the structural domain. The exceedingly large level of functional integration in today's leading edge devices challenges test strategests to innovate and to think outside the box across a broad set of issues while remaining practical and cost sensitive.

Papers & presentations should focus on new DFT methods or techniques. Papers that are practical and used in real products with backup data are particularly desired.

DFT Areas of Interest

• At speed ATPG methods and results
• Cost of Test reduction via DFT
• New fault modeling techniques
• DFT economics modeling
• BIST and embedded test
• High-speed I/O testing using DFT
• 1149.1 or 1149.6 approaches
• Debug, diagnostics, or failure analysis using DFT

Schedule

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