SiliconAid Solutions, INC.

Registration - 2005 SWDFT Tutorial Sessions

See Tutorial Descriptions Below!
Participant's Contact Info
First Name
Last Name
Job Title
Email Address
Phone Number Required Field to contact you regarding payment
Which Tutorial (1,2,3)
Method of Payment (Visa, MC, or Cash) DO NOT INSERT CARD NUMBER
Please Click the Submit Button When Ready. Please do not click twice. Thank you!

Three Tutorial Briefs

Tutorial 1 – DFT for Low Cost Test
Date: May 17th, 2005
Duration: 1 day (8 hours)
Cost: $500
Presenters: Alfred Crouch, Inovys Corporation (See Bio)

Who Should attend? IC, SOC, and IP designers, integrators , product and test engineers
Description: Instead of being just another DFT lecture, this tutorial primarily focuses on the economic, design, and test implications of DFT and the use DFT to in areas such as first silicon turn on, failure analysis, design debug, etc. The tutorial focuses at a high level, with just enough technical content to be meaningful to engineers. Using a practical approach and industry examples, this tutorial explains the characteristics and limitations of structural test methodologies, and explains how DFT focused testing fits into the design and test flow. Common DFT techniques and issues such as DC scan, AC scan, ATPG, BIST, SoC Assembly and IP reuse are explained in context of low cost test.
OUTLINE
-Introduction
-How big is the low cost test problem?
-Designing low cost tests
-Debug and Diagnostics Issues
-Manufacturing concerns
-Conclusions

==========================================================

Tutorial 2 – JTAG (IEEE 1149.1 and IEEE 1149.6)
Date: May 18th, 2005
Duration: 1/2 day (4 hours)
Cost: $250
Presenter: Bill Bruce, SiliconAid Solutions, Inc. (see Bio)
Who Should attend? IP designers, Chip/SOC integrators , product and test eng
Description: Walk out of this tutorial knowing JTAG, how it is being used now and in the future. Get a good understanding of the IEEE specifications, design considerations, implementation issues, and manufacturing concerns. Also learn the new IEEE 1149.6 specification and what you need to know it use it.
OUTLINE
-Introduction
-Overview of JTAG
-How to Implement JTAG
-Overview of 1149.6 and who needs it
-1149.6 implementation and verification issues
-Manufacturing considerations
-Conclusions

==========================================================

Tutorial 3 – Advanced Topics in DFT-Focused Test
Date: May 18th, 2005
Duration: _ day (4 hours)
Cost: $250
Presenter: Ken Posse. (see Bio)
Who Should attend? Managers, designers engineers, and product/test engineers
Description: The tutorial covers four areas in some detail: Delay Fault Testing (AC Scan), Iddq Testing, Embedded Mixed Signal testing, and the use of the IEEE 1149.1 Test Access Port as a control mechanism for embedded test circuitry.
OUTLINE
-Construction of a device from Library cells
-Failures
-Process Monitors vs Test and Failures
-Testing for Delay Faults
-Testing Quiescent Currents (iddq)
-Current Thoughts on Embedded Mixed Signal Testing
-New IJTAG Initiative