DFT Methodology Development

DFT Methodology can be developed in several approaches depending upon the customer needs and requirements. We can work with your team in an advisory capacity to enhance and augment your team. We can also do a turn key solution that develops your DFT methodology and flow around your specific design flow and goals.

Since we are an indepenent company, we can offer an unbiased opinion for the optimal flow for your goals and cost objectives.

An evaluation of the specific cost objectives and goals will be reviewed to make the design impact vs DFT and test trade-offs. Things like expected manufacturing volume and device size may influence the DFT flow. A complete flow can be developed and tested to make sure the flow generates all the correct views and files required to fit seamlessly into your design environment.

The flow can then be customized and automated to guarantee repeatable and reliable results.

DFT Automation

SiliconAid Solutions can automate your flow to execute with very little interaction required in many cases. This allows a non-DFT expert to execute some or most of the DFT steps which could include scan insertion, ATPG, MBIST insertion, and more.

Several types of scripts could be utilized depending upon the design flow and tools available. (DC shell scripts, PERL, C or C++, TCK, C-shell scripts)

For more generic flows, a web based custom interface could be generated to control the DFT steps.

Design vs Test Time & DFT Trade-offs

Depending upon the customer objective, different trade-offs might be made for your the DFT strategy.

ATPG Library Generation

Several major DFT software vendors require a custom library or modified library views for DFT. We are well versed in generating these required libraries. We can use the customer's golden verilog model or VHDl model to generate and/or verify the ATPG models. We verify by simulation that the models function correctly and match the golden models.

Companies that supply libraries or memory models may also require verification of the models supplied.

Any mismatch between the simulation library and the DFT library can cause patterns to be non-functional further down the product development cycle.

Scan Insertion, Add/Optimize Test Control Logic, and ATPG - Vector Generation

SiliconAid Solutions Inc. can provide the optimal scan implementation to obtain the highest possible test coverage at the lowest possible cost. Full scan, Partial scan or a combination of both could be used depending on the customers requirements and objectives. A full set of DFT specific DRC(Design Rules Checks) are run to help determine any issues as early in the process as possible.

Test Synthesis is the modification of the design to add scan circuitry. Some of the steps included in this phase of the development are:

ATPG Vector Generation is the creation of patterns for manufacturing testing. Some of the steps in this phase of the development are:

Additional Challenges may include:

Memory BIST Generation

Today, most devices and SOC's contain some form of embedded memory. Memory Built In Self Test (BIST) is a very efficient way to test these memories with a relatively low area and design impact.

We can analyze your specific architecture and objectives to determine how the memory BIST should be designed and implemented.

We will use our expertise to identify:

SiliconAid Solutions has extensive experience generating many different types of Memory BIST solutions. We can generate RTL level synthesizable code for the Memory BIST logic and controller(s). Our team can also help you integrate BIST logic into your design.

Logic BIST Insertion

Logic Built In Self Test (BIST) leverages a scan based design to minimize the requirements for external test stimulus or capture.

Logic BIST should be considered on :

Our team has experience in Logic BIST design and implementation. We can generate RTL level synthesizable code for the Logic BIST logic and controller(s). Our team can also help you integrate BIST logic into your design.

JTAG Generation

IEEE 1149.1 standard also referred to as JTAG or Boundary Scan is primarily for board level testing. JTAG is commonly used and can be implemented with additional functionality to control special test modes.

SiliconAid Solutions can implement a 1149.X and all associated standards compliant design and customize it for your specific design and testing requirements. The JTAG controller will be fully verified to operate correctly.

Fault Simulation and Grading

SiliconAid Solutions can take existing scan patterns or functional patterns and Fault Simulate them to determine the level of test coverage they provide. We can also generate additional patterns to improve the overall test coverage of the device.

We will produce a test coverage report describing the scan and functional patterns executed, the coverage for each pattern set, and an overall chip coverage numbers.

Manufacturing Test Program Debug assistance and Failure Analysis assistance

SiliconAid Solutions can reformat failing ATE vector data and help pin point the area and possible gates causing the failure. This type of fault isolation is invaluable in the debugging and characterization phases of the product life cycle.

While we are not test engineers, we are familiar with ATE architectures. We can work with the test engineers to help identify and correct issues.