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Hosted By


               

When : April 24th & 25th, 2008

Where : Crown Plaza Hotel, Austin TX

Who Should Attend : Anyone interested in learning more about DFT methods for practical real world chip applications. DFT engineer, Test/Product Engineers, FA engineers, middle to upper managers.

SORRY - Pre-registration is now CLOSED. You can register on site for a $25 fee.

 Event Description

This 2 day conference consists of a day of DFT class and a day open technical day. The technical day will be a mix of vendors and guest presenters. The technical day is FREE and is open to all when you pre-register on this web site. You can register for the conference now. Class registration is open on a first come first serve bases.

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FREE DFT IP Class (April 24th)

Given by three very Senior DFT experts in their fields, this FREE one day class will cover 3 IEEE standards. This Class will describe the standards needed to handle IP for our DFT world.
Location : Freescale Training Center - Parmer Lane, Austin

IEEE 1500  (Wrappers) Teresa Mclaurin (Arm)
IEEE 1450.6  (CTL language)  Rohit Kapur (Synopsys)
P1687 (IJTAG) Al Crouch (Asset Intertech)

 A full outline of the class will be added to the website in the next week or so.

Sorry - Tutorial registration is now closed!

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FREE Technical DFT Day (April 25th)

The technical day is a FREE day to web-registered attendees (extended until April 20th). On-Site registration is a fee of $25. DFT and test engineers from the semiconductor industry and the EDA community will be presenting. The day will start with a Key Note Speaker followed by 6 to 8 technical talks and presentations. We expect to exceed over 150 attendees for the final day of the event. DFT Companies will also be setting up small booth demonstrations in the hallway just outside of the main conference hall. See below for the Agenda! Location : Crown Plaza Hotel, Austin TX (6121 NORTH IH 35 )

 SORRY - Pre-registration is now CLOSED. You can register on site for a $25 fee.

                                        

April 25th, 2008                                                                     

8:00 - 8:30 On site Registration (coffee provided)
 8:30 - 8:40 Welcomes and introductions
8:40 - 9:10 Key Note Address - T.W. Williams (Synopsys)

Session 1
9:10 - 9:55 - Presentation 1  - Rob Aiken (ARM)
                  Title – Variability and Defects at Current Technology Nodes
9:55 - 10:40 - Presentation 2 – Nur Touba (University of Texas)
                  Title – DFT Test Time Reduction
10:40 - 11:15  B R E A K
Session 2           
11:15 - 12:00 - Presentation 3 – Heidi Barnes (Verigy)
                  Title – Testing High Speed Test Interfaces
 11:45 - 1:30 LUNCH - Free lunch
1:30 - 2:15 - Presentation 4 – Jimmy Wingfield (AMD)
                  Title – TAM for Multiple Identical Cores
2:15 - 3:00 - Presentation 5 – Brady Benware (Mentor Graphics)
                  Title – The Role of DFT in Yield
Session 3    
3:00- 3:45  B R E A K
3:45 - 4:30 - Presentation 6 – Carol Pyron (Freescale)
                  Title – Design Considerations for IEEE 1149.6
4:30 - 5:15 - Presentation 7 – Clark Jernigan (Austin Ventures)
                  Title – Semiconductor Business Review and Outlook
5:30 - 6:30 - Panel Discussion                       Referee: Jim Johnson
 5:30  - 6:30 Happy Hour during Panel

Vendor Booths open from 8:30am - 6pm


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