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WHEN : April 2nd & 3rd, 2009     (FREE if registered before March 27th)

Hotel information
Map To Tutorial - April 2nd (AMD - building B - Media room B500)
Map to Conference April 3rd (Omni SouthPark Hotel)

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Advanced Registration is now CLOSED - You can register on Site for $30/person

Who should take the class?

  • Managers, project leads, etc who need a basic introduction to understand the tradeoff to justify DFT and optimize Test techniques to save $$, and/or improve quality, and/or improve overall schedule.
  • DFT & Test Engineers that need to justify and persuade upper level managers to support DFT and Test
Who should not attend the class?
  • Engineers with basic DFT knowledge expecting a detailed discussion on implementing DFT.

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Advanced Registration is now CLOSED - You can register on Site for $30/person

KEY NOTE SPEAKER - Janusz Rajski - Mentor Graphics

Chief Scientist, Director of DFT Engineering

April 3rd, 2009
8:00 - 8:30 On site Registration (coffee provided)
8:30 - 8:40 Welcomes and introductions
8:40 - 9:10 Key Note Address – Janusz Rajski (Mentor Graphics)

Session 1 
9:10 - 9:50 - Presentation 1  - Grady Giles (AMD)
                  Title – Pros and Cons of Logic BIST
9:50 - 10:30 - Presentation 2  - Mohammad Tehranipoor (U of Connecticut)
                  Title – Test and Diagnostics for Timing and Power Related Failures
10:30 - 11:10  B R E A K
11:10 – 12:10 – Sponsor Presentations  - (20 min each)
                  Title – Synopsys, Mentor Graphics, WinterLogic
 12:10 - 1:30 LUNCH - Free lunch
Session 2  

1:30 – 2:10 - Presentation 4 – Chris Hawkins (ARM)
                  Title – Practical examples using a DFT tester for test chip
2:10– 2:50 - Presentation 5  - Colin Renfrew (Freescale)
                  Title – Enhancing At-Speed ATPG Using Information from STA
2:50 - 3:30 - Presentation 6  - Stephen Lau (Texas Instruments)
                  Title – IEEE 1149. 7 Overview

3:30 - 4:10  B R E A K

Session 3         

4:10 – 4:50 - Presentation 7  - Rohit Kapur (Synopsys)
                  Title – What can ATPG do for Switching Activity Reduction?
4:50 – 5:30 - Presentation 8 – Sumit Dasgupta  (SI2)
                  Title – Semiconductor Business Review and Outlook: View from Deep Inside the Trenches
5:30 - 6:30 - Panel Discussion                       Referee: Jim Johnson
 5:30  - 6:30 Happy Hour during Panel